An integral shannon-based view on smart front-ends (invited)

This paper describes how trends in information society, communication technology, microwave technology, and IC-design technology, ask for a different view on front-ends. The communication channel will be described from a high level, as one dasiaShannon channelpsila, comprising a chain of cascaded sub channels. Trends influencing each sub channel will be addressed. From that, we will argue that an integral approach to the design of the communication chain will be a prerequisite for the design of future front-ends. Moreover, the design of the front-end will become dominated by the IC part of the chain, rather than by the transmission channel, which will lead to dasiaconversion-drivenpsila rather than dasiatransmission-channel drivenpsila analog front-ends. Finally, it will be shown that future converters will have to be smart. Although applied to wireless, the conclusions are generic and as such can be applied to wired communication channels too

Shifting the frontiers of analog and mixed-signal electronics

Nowadays, analog and mixed-signal (AMS) IC designs, mainly found in the frontends of large ICs, are highly dedicated, complex, and costly. They form a bottleneck in the communication with the outside world, determine an upper bound in quality, yield, and flexibility for the IC, and require a significant part of the power dissipation. Operating very close to physical limits, serious boundaries are faced. This paper relates, from a high-level point of view, these boundaries to the Shannon channel capacity and shows how the AMS circuitry forms a matching link in transforming the external analog signals, optimized for the communication medium, to the optimal on-chip signal representation, the digital one, for the IC medium. The signals in the AMS part itself are consequently not optimally matched to the IC medium. To further shift the frontiers of AMS design, a matching-driven design approach is crucial for AMS. Four levels will be addressed: technology-driven, states-driven, redundancy-driven, and nature-driven design. This is done based on an analysis of the various classes of AMS signals and their specific properties, seen from the angle of redundancy. This generic, but abstract way of looking at the design process will be substantiated with many specific examples

Ultra high data rate CMOS FEs

The availability of numerous mm-wave frequency bands for wireless communication has motived the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performaning measurements using on-wafer probing at 60GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitiv to the effective length and bending of the interfaces. This paper presents different 60GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, A Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60GHZ integrated components and systems in the main stream CMOS technology

Ultra high data rate CMOS front ends

The availability of numerous mm-wave frequency bands for wireless communication has motivated the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performing measurements using on-wafer probing at 60 GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitive to the effective length and bending of the interfaces. This paper presents different 60 GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, a Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60 GHZ integrated components and systems in the main stream CMOS technology

A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC with signal-independent delta-I noise DfT scheme

This paper presents a 3.5GSps 6-bit current-steering DAC with auxiliary circuitry to assist testing in a 1V digital 28nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035mm2, making it suitable to embedding in VLSI systems, e.g. FPGA. To cope with the IC process variability, a unit element approach is generally employed. The 3 MSBs are implemented as 7 unary D/A cells and the 3 LSBs as 3 binary D/A cells, using appropriately reduced number of unit elements. Furthermore, all digital gates only make use of two basic unit blocks: a buffer and a multiplexer. For testing, a memory block of 5kbits is placed on-chip, which is externally loaded in a serial way but internally read in an 8x time-interleaved way. The memory is organized around 48 clocked 104-bit shift-registers. It keeps the resulting switching disturbances signal-independent and hence avoids inducing output non-linearity errors, even when a common power supply is shared with the DAC. This novelty allows reliable testing of the DAC core, while avoiding performance limitation risks of handling high-speed off-chip data streams. The DAC SFDR>40dB bandwidth is 0.8GHz, while the IM

RF Receiver front end for 28.5 GHz applications on a 70 GHz F-T SiGe BiCMOS process

This article presents the design and test of a receiver front end aimed at LMDS applications at 28.5 GHz. It presents a system-level design after which the receiver was designed. The receiver comprises an LNA, quadrature mixer and quadrature local oscillator. Experimental results at 24 GHz center frequency show a conversion voltage gain of 15 dB and conversion noise figure of 14 5 dB. The receiver operates from a 2 5 V power supply with a total current consumption of 31 mA

Noise reduction in nanometre CMOS

With nanometre scaling, the amount of transistors per 100 square millimetre will increase following Moore's Law. The maximum power will, without additional cooling, be limited to a few watt whereas the on- and off-chip clock and data speeds will increase further. To accommodate this, the core supply voltages are reduced further down to below 1 volt as where the peripheral supply voltages will have to follow international agreed voltages levels to enable interfacing. While lowering the core supply voltages, the on-chip noise margin will drop accordingly and tight on- and off-chip decoupling measures are necessary. However by application, RF switching noise from nanometre CMOS designs are forced out of their packages through the supply and ground pins when applying conventional off-chip decoupling is applied. In this paper, the state-of-the-art, as well as a new noise reduction technique, which is possible with today's nanometre CMOS processes, will be discussed together with guidance to accompanying complementary off-chip measures

An 11b pipeline ADC with dual sampling technique for converting multi-carrier signals

This paper presents a dual sampling technique for analog-to-digital converters (ADCs) to convert multi-carrier signals more efficiently and proposes an 11b switched-capacitor pipeline ADC based on this technique. With the dual sampling technique, the input signal power of the ADC can be boosted without getting excessive clipping noise and the ADC can have a higher resolution over the critical low amplitude region. Hence the overall signal to thermal, quantization and clipping noise ratio is improved. The 11b pipeline ADC with the proposed technique achieves a wide input signal range of 2Vppd using a single 1.2V supply. Simulations show an improvement of about 5dB in SNDR and better than 10dB in MTPR compared to a conventional 11b ADC for converting multi-carrier signals

A 107GHz LNA in 65nm CMOS with inductive neutralization and slow-wave transmission lines

This paper presents a 107GHz LNA prototype using TSMC 65nm CMOS technology. It explores the limit of the CMOS technology by effectively optimizing the active and passive devices. An improvement of 1.6dB higher maximum stable/available gain (MSG/MAG) on the transistor is achieved around 110GHz by layout optimization and inductor neutralization technique. A high quality factor co-planar waveguide (CPW) transmission line is designed utilizing the slow-wave effect. A quality factor of 23.6 is demonstrated by EM-simulations while taken the consideration of satisfying the stringent layout design rules. Based on the optimization on the active and passive devices, a dual-stage LNA is designed, with a simulated power gain of 10.2dB and noise figure of 8dB at 107GHz, verified by chip-level EM-simulations. The power consumption is 28.2mW